Delay generator

ABSTRACT

A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.

BACKGROUND OF THE INVENTION

The present invention relates to a delay generator. More particularly,it relates to a process-insensitive current-controlled delay generatorwith threshold voltage compensation.

DESCRIPTION OF THE RELATED ART

Sampled-data systems incorporating data conversion andswitched-capacitor filters are indispensable in state-of-art IC design,and are crucial for applications such as telecommunication, consumerelectronics and medical imaging. In such discrete-time systems, theclock generator is extremely important, and the accuracy of the clocksignal is determinant in the overall design since it often affects theoverall resolution. However, the variation of the clock pulse widthexists inevitably and is normally associated with process or temperaturevariations in the delay paths. Usually, large design margins should beadopted in the transistor implementation to overcome such processvariations. Unfortunately, this would imply extra power consumption withthe subsequent degradation of system performance.

Therefore, process-insensitive delay generators are highly demanded andeffective solutions have been proposed either off-chip or on-chip.

Traditionally, the delay generator is implemented by the inverter-chain,also referred to as g_(m)/C circuit that accumulates the time delay ofthe inverters and provides the time delay for the system. Although itsarchitecture is quite simple, it suffers from a significant processvariation sensitivity that can lead to a significant ±15% variation intime delay.

An alternative solution, the current-controlled delay generator waspreviously proposed to achieve higher process-insensitivity with theutilization of less process-sensitive circuit elements. FIG. 1 aschematically illustrates a simplified delay generator which containsbasically a current source, a capacitor, switches, and output buffers;and FIG. 1 b illustrates input and output waveforms of the delaygenerator of FIG. 1 a. The top-plate of the capacitor C is firstlycharged to the voltage supply VDD and Φ_(out) remains at HIGH level.Then, the capacitor C is linearly discharged by a constant current I_(b)which is controlled by the current source, and thus a delay t_(d) isgenerated.

To calculate the delay t_(d), firstly refer to the following equation:

$\begin{matrix}{i = {C\frac{\mathbb{d}V_{C}}{\mathbb{d}t}}} & (1)\end{matrix}$

Under a linear situation, dt≈Δt and dV_(C)≈ΔV_(C),

thus when i=I_(b); we obtain

$\begin{matrix}{{\Delta\; t} = {{C\frac{\Delta\; V_{C}}{I_{b}}} = t_{d}}} & (2)\end{matrix}$

where ΔV_(C) is equal to VDD−V_(th) (V_(th) is the threshold voltage ofthe inverter connected to Vc).

The current I_(b) is provided by the current source and its accuracy ismainly related to the precision of the current mirror and the referencecurrent. This is usually accurate and the current mirror is relativelyeasy to design with good matching. Therefore, the current will not besignificantly affected by process variations. Besides, a MOS-capacitoris adopted to ensure less sensitivity to process variations, whencompared with other type of implementations of the capacitors. Normally,the MOS-capacitance varies around ±5% with process.

However, the delay generator of FIG. 1 a is still sensitive to processvariations, mainly because of threshold voltage variation of theinverter connected to the capacitor. When V_(C) decreases, the inverterwill be triggered to generate the delay t_(d) until V_(C) passes itsthreshold voltage V_(th) that depends on the robustness of the N/PMOStransistors and is highly process-sensitive.

SUMMARY OF INVENTION

In view of the above, it is an object of the present invention toprovide an advanced current-controlled delay generator usingprocess-insensitive components such as current mirrors andMOS-capacitors, thereby avoiding the complexity of a delay-locked loop(DLL). By applying the threshold voltage compensation, the delaygenerator of the present invention reduces the deviation induced by theinternal inverter buffer, and thus becomes more robust to processvariations than prior art.

According to an aspect of the present invention, a delay generatorcomprises: a current source for supplying a current; a first delayportion, connected to the current source, comprising at least aplurality of inverters and a first capacitor having a first capacitance;and a second delay portion, connected to the current source, comprisingat least a plurality of inverters and a second capacitor having a secondcapacitance, wherein the first capacitance is the same as the secondcapacitance, wherein the first delay portion generates a first delay bydischarging of the first capacitor, wherein the second delay portiongenerates a second delay by charging of the second capacitor, andwherein the total delay generated by the delay generator is obtained bysummation of the first delay and the second delay.

According to the above aspect of the present invention, the total delayis determined by the current and the first capacitance.

According to the above aspect of the present invention, the first delayportion further comprises two switches that will be tamed on by oppositeinput clocks.

According to the above aspect of the present invention, the second delayportion further comprises two switches that will be turned on byopposite input clocks.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will become more apparent from the following description whentaken in conjunction with the accompanying drawings.

FIG. 1 a shows a simplified diagram of a delay generator according toprior art.

FIG. 1 b illustrates input and output waveforms of the delay generatorof FIG. 1 a.

FIG. 2 shows a block diagram of a delay generator according to thepresent invention.

FIG. 3 illustrates input and output waveforms of the delay generatoraccording to the present invention.

FIG. 4 shows the circuit implementation of the delay generator accordingto the present invention.

FIG. 5 a shows the characteristic waveforms for a first delay portion ofthe delay generator according to the present invention.

FIG. 5 b shows the characteristic waveforms for a second delay portionof the delay generator according to the present invention.

FIGS. 6 a and 6 b show characteristic waveforms of the delay generatoraccording to the present invention in a typical case and two extremecases.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment for a delay generator according to the inventionis described with reference to the drawings as follows.

Refer firstly to FIG. 2, which illustrates an embodiment of acurrent-controlled delay generator 200 according to the invention. Inthis embodiment, the delay generator 200 comprises a current source 210,a first delay portion 220 and a second delay portion 230. The currentsource 210 provides a current I_(b) to both the first delay portion 220and the second delay portion 230. An input clock Φ_(in) in is fed intothe first delay portion 220 and an output clock Φ_(middle) having adelay t_(d1) with respect to the clock Φ_(in) is generated. Next, theclock Φ_(middle) is fed into the second delay portion 230 and an outputclock Φ_(out) having a delay t_(d2) with respect to the clock Φ_(middle)is generated. As a result, the total delay t_(dtotal) generated by thedelay generator 200 is obtained as t_(d1)+t_(d2). A schematic diagramshowing the total delay t_(dtotal)=t_(d1)+t_(d2) is shown in FIG. 3. Thetotal delay t_(dtotal) generated by the delay generator 200 isinsensitive to the process variation because the process variationincurred when t_(d1) is generated and the process variation incurredwhen t_(d2) is generated will be compensated by each other. A furtherdetail for achieving the compensation effect of the process variationaccording to the present invention is described as follows.

The circuit of FIG. 4 represents a preferred embodiment of the delaygenerator 200. As shown in the figure, the delay generator 200 iscomprised of the first delay portion 220 and the second delay portion230. Although, in FIG. 4, the current source 210 is shown as included inthe first delay portion 220, the current I_(b) is also provided to thesecond delay portion 230 through the bias point Vbn.

The operation of the first delay portion 220 can be divided into twophases. At the first phase, the clock Φ_(in) is going from LOW to HIGH,the switch S1 is open (turned off) and the switch S2 is closed (turnedon). Accordingly, a transient current will charge a capacitor C1 untilthe top-plate voltage V_(C1) of the capacitor C1 reaches VDD. Next, atthe second phase, the clock Φ_(in) is going from HIGH to LOW, the switchS1 is closed (turned on) and the switch S2 is open (turned off). BecauseV_(C1) has been charged to VDD, the voltage V_(tr1) (which is obtainedfrom V_(C1) after two inverters) will be VDD, too. Thus, M3 connects anda discharging current begins to flow. The current mirror comprised of M1and M2 renders the discharging current equal to I_(b). The charge storedon the top plate of the capacitor C1 flows to the ground through S1, M3and M2, and thus the voltage V_(C1) starts dropping. When V_(C1) reachesthe threshold voltage V_(th) (triggering point) of the inverter, V_(tr1)becomes digital ‘0’ and thus shuts off M3. At this moment, thedischarging current stops flowing from C1 and V_(C1) remains the same.The above discharging operation generates a delay t_(d1), and thus theclack Φ_(middle) is output, as clearly illustrated in FIG. 5 a.Subsequently, the operation returns to the first phase, V_(C1) will becharged to VDD again and V_(tr) also goes to VDD by rapid pull-up of theinverter.

As shown in FIG. 5 a, V_(C1) is dropping linearly. Accordingly, byreferring to the above-mentioned equation (2), t_(d1) can be expressedas:

$\begin{matrix}{t_{d\; 1} = {C\; 1\frac{V_{th} - {VDD}}{- I_{b}}}} & (3)\end{matrix}$

Similarly, the operation of the second delay portion 230 can be dividedinto two phases. For the second delay portion 230, the clock Φ_(middle)is inverted and used as an input clock. At the first phase, the clock Φ_(middle) is going from HIGH to LOW, the switch S3 is open (turned off)and the switch S4 is closed (turned on). Accordingly, C2, which has acapacitance as the same as that of C1, will be discharged through theswitch S4 and reset to ground. Next, at the second phase, the clock Φ_(middle) is going from LOW to HIGH, the switch S3 is closed (turned on)and the switch S4 is open (turned off). Accordingly, C2 is charged by aconstant current from a p-type current mirror comprised of M6 and M7,and the voltage V_(C2) starts raising from 0 (ground). When V_(C2)reaches the threshold voltage V_(th) (triggering point) of the inverter,V_(tr2) becomes digital ‘0’ and thus shuts off M8. At this moment, thecharging current stops flowing to C2 and V_(C2) remains the same. Theabove charging operation generates a delay t_(d2), and thus the clockΦ_(out) is output, as clearly illustrated in FIG. 5 b.

As shown in FIG. 5 b, V_(C2) is raising linearly. Again, by referring tothe above-mentioned equation (2), t_(td2) can be expressed as:

$\begin{matrix}{t_{d\; 2} = {C\; 2\frac{V_{th} - 0}{I_{b}}}} & (4)\end{matrix}$

As mentioned above, the total delay t_(dtotal) generated by the delaygenerator 200 is obtained by summation of t_(d1) and t_(d2), that is,t_(d1)+t_(d2). From equations (3) and (4), we obtain:

$\begin{matrix}{t_{dtotal} = \frac{{\left( {{C\; 1} - {C\; 2}} \right)V_{th}} + {C\; 1 \times {VDD}}}{I_{b}}} & (5)\end{matrix}$

As C1=C2, it leads to,

$\begin{matrix}{t_{dtotal} = \frac{C\; 1 \times {VDD}}{I_{b}}} & (6)\end{matrix}$

Since C1, VDD and I_(b) are all preset values, t_(dtotal) will be aconstant. In other words, the total delay t_(dtotal) is not affected bythe threshold voltage V_(th), which is highly process-sensitive.

To further explain the threshold voltage compensation applied by thepresent invention, refer now to FIGS. 6 a and 6 b, whereincharacteristic waveforms of the delay generator according to the presentinvention are illustrated in a typical case (‘tt’) and two extreme cases(‘fs’: fast NMOS and slow PMOS, ‘sf’: slow NMOS and fast PMOS). The twoextreme cases are provided as examples of process corners which willproduce most significant drifts in the threshold voltage V_(th). Asshown in the figures, waveforms similar to those of FIG. 5 a and 5 b canbe observed for the typical case (process corner ‘tt’). For the ‘fs’process corner, a shorter t_(d1,fs) and a longer t_(d2,fs) can beobserved For the ‘sf’ process corner, a longer t_(d1,sf) and a shortert_(d2,sf) can be observed. However, both the summation of t_(d1,fs) andt_(d2,fs) and the summation of t_(d1,sf) and t_(d2,sf) will lead to thesame total delay t_(dtotal) as that of the typical process corner ‘tt’.In other words, the shorter t_(d1,fs) is “compensated” by the longert_(d2,fs), and the longer t_(d1,sf) is “compensated” by the shortert_(d2,sf). This is not difficult to derive because, according to theabove equation (6), the same total delay t_(dtotal) will be obtained foreither the ‘fs’ process corner or the ‘sf’ process corner.

While the present invention has been described with reference to apreferred embodiment, it will be understood by those skilled in the artthat various changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the invention.Therefore, it is intended that the invention will include allembodiments falling within the scope of the appended claims.

The invention claimed is:
 1. A delay generator, comprising: a first delay portion comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion comprising at least a plurality of inverters and a second capacitor having a second capacitance; a current source for providing a current to the first delay portion and the second delay portion, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.
 2. The delay generator according to claim 1, wherein the total delay is determined by the current and the first capacitance.
 3. The delay generator according to claim 1, wherein the first delay portion further comprises two switches that will be turned on by opposite input clocks.
 4. The delay generator according to claim 1, wherein the second delay portion further comprises two switches that will be turned on by opposite input clocks. 